Presentation Information
[A-6-01]A circuit design for mitigating aging-induced performance degradation
〇Yukiya Miura1, Orito Matsudo1 (1. Tokyo Metropolitan Univ.)
Keywords:
transistor aging (BTI,CHC),propagation delay improvement,digitally controlled oscillator,adaptive circuit design
As CMOS integrated circuits scale down, reliability issues such as BTI and CHC effects become critical concerns. These aging mechanisms cause shifts in the transistor threshold voltage leading to increased propagation delays that can cause functional failures. Traditional guard-banding manages these risks by adding design margins; however, it often incurs excessive design costs or leads to premature failures due to non-uniform degradation. To overcome these limitations, this paper proposes an adaptive circuit configuration that dynamically compensates for operating speed degradation through post-silicon adjustments.