[A-6] VLSI Design Technologies

8:45 AM - 9:00 AM JST(11:45 PM - 12:00 AM UTC)

[A-6-01] A circuit design for mitigating aging-induced performance degradation

〇Yukiya Miura¹, Orito Matsudo¹ (1. Tokyo Metropolitan Univ.)

Keywords:

transistor aging (BTI,CHC),propagation delay improvement,digitally controlled oscillator,adaptive circuit design

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