Session Details
[A-6]VLSI Design Technologies
Fri. Sep 25, 2026 8:45 AM - 10:00 AM JST
Fri. Sep 25, 2026 11:45 PM - 1:00 AM UTC
Fri. Sep 25, 2026 11:45 PM - 1:00 AM UTC
Faculty of Information Science and Technology Bldg A-33(Hokkaido University)
Chair:YUTAKA MASUDA
[A-6-01]A circuit design for mitigating aging-induced performance degradation
〇Yukiya Miura1, Orito Matsudo1 (1. Tokyo Metropolitan Univ.)
[A-6-02]イジングモデルアニーリングの高効率RB型LSI実装
◎Yu Akatsuka1, Kazuhito Ito1 (1. Saitama University)
[A-6-03]Optimization of Soft-Error Resilience in LSIs with Hybrid Redundancy
◎Taichi Goyashiki1, Kazuhito Ito1 (1. Saitama University)
[A-6-04]An Operation Mapping-Scheduling Method for Register-Bridge LSIs using HGNN and Reinforcement Learning
〇Kengo Yamashiro1, Kazuhito Ito1 (1. Saitama University)
[A-6-05]Peak Power Reduction Using Current-Limited Inverter in C-Element-Based Cryo-HT
◎Maiko Higuchi1, Hajime Takayama1, Michihiro Shintani1 (1. Kyoto Institute of Technology)
