[B-4] Electromagnetic Compatibility

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)Candidate for Academic Incentive Award

[B-4-42] Quantitative Evaluation of Signal Integrity Degradation Factors Using Design of Experiments in DDR4 Fly-by Topologies

◎Kosei Nagahara¹, Goro Hamamoto^2,1, Hiroto Miyake¹, Masahiro Yoshida¹, Yoshitaka Toyota¹ (1. Okayama Univ., 2. Hitachi)

Keywords:

Fly-by Topologies,Design of Experiments,Signal Integrity,DDR,Orthogonal Array,Analysis of Variance

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