[B-5] Ferroelectric FET 2

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[B-5-03] Tunneling Dielectric Layer Position Optimization and Performance Trade-offs in FeFETs for Fe-NAND Application

〇Zeqi Chen^1,2,3, Xianzhou Shao^1,2, Ruoyao Ji^1,2, Mingkai Bai^1,2,3, Xinpei Jia^1,2, Tao Hu^1,2,3, Junshuai Chai^1,2, Hao Xu^1,2, Xiaolei Wang^1,2, Wenwu Wang^1,2, Tianchun Ye^1,2 (1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences (CAS), Beijing, China (China), 2. Inst. of Microelectronics of Chinese Academy of Sci. (IMECAS), Beijing, China (China), 3. School of Integrated Circuits, Univ. of Chinese Academy of Sci. , Beijing, China (China))