Session Details
[PS-01]01: Advanced CMOS: Material Science / Process Engineering / Device Technology
Wed. Sep 16, 2026 3:00 PM - 5:00 PM JST
Wed. Sep 16, 2026 6:00 AM - 8:00 AM UTC
Wed. Sep 16, 2026 6:00 AM - 8:00 AM UTC
Poster Hall（Convention Hall 3+4）(Convention Hall 3+4, 2rd Floor)
[PS-01-01]Implementing Single Transistor Logic and Memory with Dual-Source/Drain RFET
〇Sandeep Semwal1, Pin Su1, Abhinav Kranti2 (1. Institute of Electronics, National Yang Ming Chiao Tung University (NYCU) (Taiwan), 2. Indian Institute of Technology Indore (India))
[PS-01-02]Drain-Polarity-Controlled RFET Using Drain-Offset Electrostatic Modulation
〇Seung-Hwa Choi1, Seung-Hyun Lee1, Won-Ju Cho1 (1. Kwangwoon Univ. (Korea))
[PS-01-03]High-Performance NC-RFGAAFETs Utilizing Hf0.3Zr0.7O2 Superlattice Dielectric for Low Power Cryogenic Application
〇Chia-Yi Lin1, Cheng-Yueh Cheng1, Yueh-Chun Wu1, Chao-Wei Wu1, Hsin-Hui Hu2, Yung-Chun Wu1 (1. National Tsing Hua Univ. (Taiwan), 2. National Taipei Univ. of Technology (Taiwan))
[PS-01-04]Investigation into Asymmetric Signal Track Allocation of Dual-sided CFET
〇Xingjian Mao1, Rui Guo1, Haoran Lu1, Runsheng Wang1, Xia An1, Heng Wu1 (1. Peking University (China))
[PS-01-05]Interconnect Routing Optimization for High-Performance CFET 6T-SRAM
〇Jimyoung Lee1,2, KwangYoung Lee1, Minhyung Kang1,2, Jongwook Jeon2 (1. Samsung Electronics (Korea), 2. Sungkyunkwan Univ. (Korea))
[PS-01-06]Process Driven Optimization of Channel Strain Retention in Vertically Stacked CFETs
Sumant Sarkar1, 〇Timothy Yang2, Tom Mountsier1, Benjamin Vincent3 (1. Lam Research, USA (USA), 2. Lam Research, Japan (Japan), 3. Lam Research, France (France))
[PS-01-07]Mechanical Stability and Adhesion of Nanosheets under Capillary Forces during the Wet Processes in Gate-all-around FETs Fabrication
〇Kenzo Manabe1, Chia-Tsong Chen1, Toshihiro Narushima1, Ryutaro Nishino1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1. National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[PS-01-08]Unraveling Intrinsic Multitrap Capture Kinetics from Stochastic Drain-Current Transients
〇Dokyoung Lee1, Sungho Kim1 (1. Ewha Womans Univ. (Korea))
[PS-01-09]Monolithic 3D Heterogeneous MoS2-Si Integration for Memory-in-LogicApplications: Common-Gate CFETs and Multibit 2T eDRAM
Jin-Kai Lin1, 〇Li-Hsuan Li1, Chao-Hui Yeh1, Chih-Chao Yang2 (1. National Tsing Hua University (Taiwan), 2. Taiwan Semiconductor Research Institute (Taiwan))
[PS-01-10]Thickness-Dependent Phonon-Limited Electron Mobility in Si (001) Films from First-Principles Calculations
〇Yi-Hsin Tu1, Gengchiau Liang1 (1. The Univ. of National Yang Ming Chiao Tung (Taiwan))
[PS-01-11]Performance Analysis of Dimple Structure in MINFIS FE-NAND Flash Memory
〇Jesun Park1, Myounggon Kang1 (1. University of seoul (Korea))
[PS-01-12]Band-edge-controlled Schottky barriers at ICO:H/Ge interfaces revealed by temperature-dependent C–V analysis
〇Tatsuro Maeda1, Hiroyuki Ishii1, Rahmat Hadi Saputro1, Chia-Tsong Chen1, Takashi Koida1, Wen Hsin Chang1 (1. National Institute of Advanced Industrial Science and Technology (Japan))
[PS-01-13]Significant performance improvement of GeSn-based RTD through interface planarization by Ge buffer introduction and H2 pressure control in MBE
〇Shigehisa Shibayama1, Shota Torimoto1, Mitsuo Sakashita1, Masashi Kurosawa1, Osamu Nakatsuka1,2 (1. Grad. Sch. of Eng., Nagoya Univ. (Japan), 2. IMaSS, Nagoya Univ. (Japan))