The advantages of Si/Ge core-shell nanowires (NW) heteroarchitectures have garnered significant interest in high electron/hole mobility transistor (HEMT) applications. Low impurity scattering in undoped Ge shell and enhancing hole gas accumulation by various Si/Ge heterostructural designs facilitates efficient conduction for charge carriers as the transistor's channel. These lead to superior electrical characteristics, including heightened carrier mobility and conductivity, thereby substantially improving transistor functionality. In this study, SiNWs formed by vapor-liquid-solid (VLS) growth using Al catalysts were applied for the creation of Si/Ge core-shell heterostructures. The vertical-aligned SiNWs with smooth surfaces and single crystalline properties are targeted while addressing the issue of metal catalyst contamination. Various designs of p-Si/i-Ge core-shell heterostructures with the addition of intermediate or/and outermost B-doped p+-Si shell were investigated to maximize hole gas accumulation in the Ge channel layer, with a focus on monitoring their core-shell structures, interfaces, and crystalline properties.