[21a-A202-1~11] 17.3 Layered materials

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[21a-A202-8] 30-50-nm-thick WSe₂ back-channel pFETs with WO_x S/D self-aligned to top gate

〇Ryosuke Kajikawa¹, Takamasa Kawanago², Iriya Muneta¹, Takuya Hoshii¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1.Tokyo Inst., 2.FIRST)

Keywords:

WSe2,Self-aligned process