[22a-A401-1~12] 8.2 Plasma deposition of thin film, plasma etching and surface treatment

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[22a-A401-11] Development of polymer fine via etching technology for 3D chiplet integration

〇Fumito Ootake¹, Yasuhiro Morikawa¹, Yoichiro Kurita² (1.ULVAC, 2.Tokyo Tech.)

Keywords:

dry etch,chiplet integration,fine via etch

Compared to the conventional semiconductor packaging technology, there are great expectations for an architecture called "chiplet integration", which consists of densely coupled circuit chip aggregates. Especially, for die-to-die high bandwidth communications over long distances (approx. 5 mm), we need multilayer fine RDL with low-Dk / Df and higher reliability. The "RDL Bridge" structure of the front-end processing design rules and low-Dk dielectric polymer can solve conventional issues. The micro-via of low Dk / Df polymer is needed to realize high performance RDL bridge. In this study, we are focused on the plasma dry etching technology. As a result, an anisotropic fine via etching profile with an etched depth of 4.0 um, an aspect ratio of 2 was achieved using by plasma dry etch.