[23p-12J-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[23p-12J-8] Study on Cu CMP Corrosion Depending on Underlayer Line Structure

〇Yuya Naito¹, Wada Junya¹, Hiroshi Itokawa¹, Masayoshi Tagami¹, Norio Ohtani¹, Masaru Kito¹ (1.KIOXIA Corporation)

Keywords:

CMP,corrosion,underlayer line

The Cu CMP process is a technology to integrate Cu in BEOL interconnects for VLSI and recess control at the several-nm level is required. The Cu recess is generated from Cu corrosion has been reported. In this conference, the result of a systematic investigation of Cu corrosion dependence on the underlayer line structure will be presented.