[24p-71B-1~8] Spintronics Technology: Frontiers of Tunnel Magnetoresistance Research and Memory Applications

3:25 PM - 3:55 PM JST(6:25 AM - 6:55 AM UTC)

[24p-71B-5] Process Technologies for High-Performance MRAM Cells

〇Shoji Ikeda^1,2, Hiroaki Honjo¹, Tetsuo Endoh^1,2,3,4 (1.Tohoku Univ. CIES, 2.Tohoku Univ. CSIS, 3.Tohoku Univ., 4.Tohoku Univ. RIEC)

Keywords:

MRAM

Currently, foundries are mass-producing embedded STT-MRAM as an alternative to eFlash in the 22/28nm CMOS generation using STT-MRAM cell technology based on interfacial perpendicular magnetic anisotropy, and the market for applications utilizing the MRAM (such as smartwatches, IoT microcontrollers, etc.) is emerging. In addition, research and development is underway at the 14/16nm generation for SRAM replacement and eFlash replacement for automotive applications. In order to apply MRAM technology to the cutting-edge Xnm CMOS generation in the future, it will be necessary to miniaturize the MRAM cell size to match the CMOS interconnect layer design rule scaling, while satisfying various application specifications and ensuring 400 degree C thermal tolerance at BEOL. In this presentation, I will review examples of STT-MRAM and SOT-MRAM cell technology development for higher performance MRAM.