[10p-N302-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

[10p-N302-8] Evaluation of dual damascene patterning by nanoimprint lithography

〇Ryosuke Hamamoto¹, Kenta Suzuki¹, Tetsuya Ueda¹, Yoshihiro Hayashi¹, Wataru Mizubayashi¹, Masaki Ishida², Hiromi Hiura², Masayuki Kagawa², Atushi Kusaka², Makoto Ogusu², Kiyohito Yamamoto² (1.AIST SFRC, 2.Canon)

Keywords:

nanoimprint,dual damascene,BEOL

This study evaluates the application of Nanoimprint Lithography (NIL) to the dual damascene (DD) process in multi-level interconnects. The use of a multi-level template that enables simultaneous formation of interconnect and via structures demonstrated potential for reducing process steps compared to conventional optical lithography. We describe the NIL technology, the DD process and the multi-level template employed in this study, and report on the patterning accuracy of the resulting interconnect and via structures.