[7p-S202-1~12] 23.1 Joint Session N "Informatics"

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[7p-S202-5] Machine learning model design focusing on error accumulation structure in multi-stage semiconductor manufacturing process

〇Takumi Yamada¹, Kentaro Kutsukake^1,2, Shunta Harada^1,2, Toru Ujihara^1,2 (1.Grad. Sch. Eng., Nagoya Univ., 2.IMaSS Nagoya Univ.)

Keywords:

error accumulation,machine learning,multi-stage process

When machine learning is applied to a multi-stage process such as a semiconductor manufacturing process, it is known that the prediction errors that occur at each stage accumulate, and the final prediction accuracy declines, but effective methods for suppressing these errors are still under study. In this study, we focused on the structure of the input distribution, analyzed the causes of error accumulation, and examined methods to suppress the accumulation of errors.