Presentation Information
[8a-N324-6]Study of wafer thinning process using Minimal Fab
〇Hiroyuki Tanaka1, Hiroshi Tokunaga2, Yoshiyuki Nozawa3, Toshihiro Hayami3, Hiroshi Sugiyama4, Noriko Miura1, Shinichi Ikeda1, Shiro Hara1,4 (1.AIST, 2.MTC, 3.SPPT, 4.HS)
Keywords:
Interposer,Packaging,Thinning
The packaging process is evolving into a semiconductor processing technology for the front-end process. We attempted to apply the technology cultivated in the front-end process of minimal equipment to the back-end process of semiconductor packaging. As one example, we focused on Si interposers. Manufacturing using by minimal fab is meaningful for low-volume, high-mix chiplet prototyping and also leads to improvements in packaging technology. First, we devised a Si interposer process specialized for thinning the Si substrate and investigated the Si bridge process technology. Then, we report on this.