[9a-S203-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[9a-S203-8] Process Flow Optimization for GAAFET Using Profile Simulator

〇Yoko Tanaka¹, Kenzo Manabe¹, Atsushi Yagishita¹, Masanaga Fukasawa¹, Toshifumi Irisawa¹, Yoshihiro Hayashi¹ (1.AIST SFRC)

Keywords:

semiconductor,GAAFET,profile simulator

The Gate-All-Around MOSFET (GAAFET) has complex shapes and is constructed from a variety of material layers, leading to numerous trade-offs during the GAAFET process. We focus on a critical trade-off between the protection of the Dummy Gate and the lowering of Fin side-wall spacer height, and we optimize the conditions using a profile simulator. We also present the results obtained by applying the optimized conditions to the actual GAAFET process.