[14p-P10-1~25] Symposium on Research and Human-Capital Development Activities aimed at Creating Next-Generation Semiconductors Industry

English Presentation

[14p-P10-25] Die-Level 3D-IC Fabrication Technology for 3D Heterogeneous Chiplet Integration

〇(D)Jiayi Shen¹, Chang Liu¹, Tetsu Tanaka^1,2, Takafumi Fukushima^1,2 (1.Graduate School of Engineering, Tohoku Univ., 2.Graduate School of Biomedical Engineering, Tohoku Univ.)

Keywords:

Die-level process,3D-IC/TSV,Chiplets

This paper presents a cost-effective die-level TSV process for rapid prototyping of 3D-ICs from commercially available 2D-ICs called shuttle dies that are manufactured in foundry services. The 3D integration process employs advanced via-last TSV formation with temporary bonding/debonding and magnetron sputtering for high-aspect-ratio barrier/seed metal deposition without long-through ionized PVD. In this work, we successfully demonstrate heterogeneous 3D integration of a micro-LED array that is stacked on a 40-um-thin 3D-IC with Cu-TSVs.