[16p-K306-1~11] FS.1 Focused Session "AI Electronics"

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[16p-K306-10] Study on efficient combinations of FeFETs with different timing of gate and substrate inputs for FeFET reservoir computing

〇Eishin Nako¹, Kasidit Toprasertpong¹, Ryosho Nakane¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

Keywords:

reservoir computing,FeFET

Previous studies have demonstrated that, in reservoir computing (RC) using ferroelectric FETs (FeFETs), combining FeFETs with pulse inputs to the gate terminal and delayed pulse inputs to the substrate terminal can enhance short-term memory characteristics and nonlinearity. In this study, we studied various combinations of FeFETs, including cases where the gate input is delayed relative to the substrate input, and compared their performance in RC.