[17a-K101-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)English Presentation

[17a-K101-10] Component Prioritization Assessment in Gate-All-Around Nanosheet FETs using Design-Technology Co-Optimization (DTCO)

〇(D)Xiaoran Mei¹, Yaoping Xiao¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS, The Univ. of Tokyo, 2.d.lab, The Univ. of Tokyo)

Keywords:

Nanosheet,DTCO,ring oscillator

Advanced CMOS device, notably Gate-All-Around (GAA) Nanosheet and Complementary FET (CFET), are crucial in navigating post-Moore era's challenges, such as quantum confinement and lithography limitations. Leading entities such as IMEC[1][2], TSMC[3], and Samsung[4][5] are advancing innovations in device characteristics and parasitic capacitance optimization across Middle-End-Of-Line (MEOL) and Back-End-Of-Line (BEOL). This study enhances a 5-track 3nm Nanosheet-based inverter cell and ring oscillator (RO) using Design-Technology Co-Optimization (DTCO), achieving performance and power enhancements of 7.7% and 10.2%, respectively. A novel component analysis by Multiple Regression Analysis (MRA) further identifies C_MEOL (MEOL capacitance) and device strategies as key factors for improving RO efficiency.