Session Details

[17a-K101-1~13]13.5 Semiconductor devices/ Interconnect/ Integration technologies

Mon. Mar 17, 2025 9:00 AM - 12:30 PM JST
Mon. Mar 17, 2025 12:00 AM - 3:30 AM UTC
K101 (Lecture Hall Bldg.)
Hitoshi Wakabayashi(Institute of Science Tokyo)
PRSonySemiconductor

[17a-K101-1]Initial growth mechanism of ALD-TiN on HfO2 in ultra-thin high-k/metal gate stacks for gate-all-around (GAA) MOSFET

〇Yukinori Morita1, Kenzo Manabe1, Hiroyuki Ota1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()

[17a-K101-2]Effect of F on the Effective Work Function of TiN/TiAlC Metal Gates for Advanced Gate-all-around FET

〇Kenzo Manabe1, Kazuya Uejima1, Hiroyuki Ota1, Yukinori Morita1, Atsushi Yagishita1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()

[17a-K101-3]Development of a Tungsten Electrode for Advanced 300 mm Silicon Processes

〇Naoya Okada1, Hiroyuki Ota1, Kenzo Manabe1, Yukinori Morita1, Toshifumi Irisawa1, Fuminori Ito1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()

[17a-K101-4]Gate Patterning by Electron Beam Lithography using a Tone Reversal Process (EB-R) Highly Compatible to Self-Aligned Double Patterning (SADP) Process

〇SUNGWON YOUN1, Tetsuya Ueda1, Motoharu Shichiri1, Junichi Furukawa1, Kazuyuki Matsumaro1, Hiroshi Hiroshima1 (1.AIST)
Comment()

[17a-K101-5]Local interconnect process using nanoimprint lithography

〇Kenta Suzuki1, Tetsuya Ueda1, Yuji Kasashima1, Masanaga Fukasawa1, Hiroshi Hiroshima1, Yoshihiro Hayashi1, Masaki Ishida2, Tomomi Funayoshi2, Hiromi Hiura2, Masayuki Kagawa2, Noriyasu Hasegawa2, Kiyohito Yamamoto2 (1.SFRC, AIST, 2.Canon)
Comment()

[17a-K101-6]Development of STI CMP process technology for GAAFET

〇Yuji Kasashima1, Takashi Matsukawa1, Atsushi Yagishita1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()

[17a-K101-7]Removal of fluorinated polymer film on semiconductor substrates by UV/Dry Air treatment

〇(M1)Kohei Koishi1, Tomonari Ogata2, Takeshi Momose1, Mitsuru Sasaki1 (1.Sci. Tech. Kumamoto Univ., 2.KIDO Kumamoto Univ.)
Comment()

[17a-K101-8]Effects of Flexural Acoustic (ZA) Phonon on the Electron Mobility in Silicon Nanosheet

〇(P)Hikaru Horii1, Akiko Ueda1, Yoshihiro Hayashi1 (1.AIST)
Comment()

[17a-K101-9]Spectroscopic ellipsometry characterization of extremely thin Si film
for nano-sheet FET process

〇Naoto Kumagai1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()

[17a-K101-10]Component Prioritization Assessment in Gate-All-Around Nanosheet FETs using Design-Technology Co-Optimization (DTCO)

〇(D)Xiaoran Mei1, Yaoping Xiao1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, The Univ. of Tokyo, 2.d.lab, The Univ. of Tokyo)
Comment()

[17a-K101-11]Design Technology Co-optimization (DTCO) for spacer Design in Gate-All-around Nanosheet FETs

〇(M2)Yaoping Xiao1, Xiaoran Mei1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)
Comment()

[17a-K101-12]Comprehensive Study on the Silicon-Nanosheet Thickness Dependence On the Device Performance of Gate-All-Around NFETs

〇(M2)Yaoping Xiao1, Xiaoran Mei1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)
Comment()

[17a-K101-13]Analytical modeling of RTN-induced current distribution with short dwell time

〇Kazuya Uejima1, Kenzo Manabe1, Yoshihiro Hayashi1 (1.SFRC, AIST)
Comment()