[15a-M_124-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[15a-M_124-2] Demonstration of Layer Selective Control in 3D Vertically Stacked Silicon Quantum Dots with Shared Barrier Gates

〇(D)Daiki Futagi¹, Jun-Oh Kim¹, Tomoko Mizutani¹, Takuya Saraya¹, Hiroshi Oka², Takahiro Mori², Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS. UTokyo., 2.AIST)

Keywords:

Qubits,quantum dots,Si MOSFET

We report a layer-selective control method for 3D stacked silicon quantum dots (Si QDs). We fabricated a two-layer stacked device with a shared barrier gate (BG) and performed cryogenic measurements. By utilizing the difference in sensitivity of each layer to the BG, we achieved separation between the top and bottom layers QD in a shared-gate architecture. Furthermore, we confirmed that the Coulomb peak positions of each layer can be controlled using substrate bias and BG voltage.