The 73rd JSAP Spring Meeting 2026
Advanced Search

Session Details

Oral presentation13 Semiconductors : 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[15a-M_124-1~13]13.5 Semiconductor devices/ Interconnect/ Integration technologies

Sun. Mar 15, 2026 9:00 AM - 12:30 PM JST
Sun. Mar 15, 2026 12:00 AM - 3:30 AM UTC
M_124 (Main Bldg.)
9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)

[15a-M_124-1]Layer-Dependent Transport in Two-Layer Vertically Stacked Silicon Quantum Dots via Substrate Bias

〇(D)Junoh Kim1, Daiki Futagi1, Tomoko Mizutani1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.IIS, Univ. of Tokyo, 2.AIST)
9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[15a-M_124-2]Demonstration of Layer Selective Control in 3D Vertically Stacked Silicon Quantum Dots with Shared Barrier Gates

〇(D)Daiki Futagi1, Jun-Oh Kim1, Tomoko Mizutani1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.IIS. UTokyo., 2.AIST)
9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[15a-M_124-3]Impact of Device and Integrated Structures on State Readout Sensitivity of Silicon Spin Qubits

〇Shota Iizuka1, Hidehiro Asai1, Kimihiko Kato1, Takumi Inaba1, Satoru Miyamoto1, Hiroshi Oka1, Takashi Nakayama1, Takahiro Mori1 (1.AIST)
9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[15a-M_124-4]Evaluation of Quantum Capacitance in Ge Quantum Well for Parametric Amplification

〇(M2)Bo Jiang1, Yuto Arakawa1, Chutian Wen1, Ryutaro Matsuoka1, Raisei Mizokuchi1, Tetsuo Kodera1 (1.Science Tokyo)
10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)English Presentation

[15a-M_124-5]Reinvestigation on Subthreshold Swing of Gate-All-Around Nanosheet FETs in
Quantum Limit for Voltage Scaling

〇Yaoping Xiao1, Yuxuan Wang1, Xiaoran Mei1, Tomoko Mizutani1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1 (1.IIS, Univ. of Tokyo)
10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)

[15a-M_124-6]Dependence of Characteristics on Crystral Orientation and Channel Direction in Multi-Channel GAA MOSFETs

〇(M2)Ryusei Shimoda1, Jun-Oh Kim1, Daiki Futagi1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Univ. Tokyo)
10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[15a-M_124-7]Study of TD(Tunnel-Dielectric) TFT with graphene/Si nanosheet structure

〇Naoto Matsuo1, Akira Heya1, Koji Sumitomo1, Kazushige Yamana1, Tetsuo Tabei2 (1.Univ. Hyogo, 2.Hiroshima Univ.)
11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[15a-M_124-8]Characterization of Cryogenic GeOI FinFET CMOS

〇WENHSIN CHANG1, X. R. YU2, Y. J. LEE3,4, Y. H. WANG2, T. MAEDA1 (1.AIST, 2.NCKU, 3.TSRI, 4.NYCU)
11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[15a-M_124-9]Vertically Stacked P-3NS/N-3NS Ge CFET

〇Tatsuro Maeda1, F. J. Chu2,3, Y. J. Lee2,4, Y. H. Wang3, W. H. Chang1 (1.AIST, 2.TSRI, 3.NCKU, 4.NYCU)
11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)English Presentation

[15a-M_124-10]Study on Design-Technology Co-Optimization for Complementary FET Logic

〇(D)Yuxuan Wang1, Yaoping Xiao1, Jinhyun Chun1, Xiaoran Mei1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1 (1.IIS, The University of Tokyo)
11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)English Presentation

[15a-M_124-11]Design–Technology Co-Optimization (DTCO) for Inner-Spacer Length Design
in Nanosheet Standard Cells Using a Pseudo Logic-Block Gauge

〇(D)Xiaoran Mei1, Yaoping Xiao1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)
12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)

[15a-M_124-12]Critical Charge Characteristics of CFET SRAM under Single-Event Conditions

〇Koichi Fukuda1, Junichi Hattori1, Shinichiro Abe2, Masanobu Hashimoto3 (1.AIST, 2.JAEA, 3.Kyoto Univ.)
12:15 PM - 12:30 PM JST(3:15 AM - 3:30 AM UTC)

[15a-M_124-13]TCAD simulation of single-trap-charge-induced variability in gate-all-around nanosheet silicon channel

〇Takefumi Kamioka1, Junichi Hattori1, Naoya Okada1, Koichi Fukuda1 (1.SFRC, AIST)
Back to Category List