[15a-M_124-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[15a-M_124-9] Vertically Stacked P-3NS/N-3NS Ge CFET

〇Tatsuro Maeda¹, F. J. Chu^2,3, Y. J. Lee^2,4, Y. H. Wang³, W. H. Chang¹ (1.AIST, 2.TSRI, 3.NCKU, 4.NYCU)

Keywords:

Ge,nanosheet,CFET

Complementary FETs (CFETs), which vertically stack pFETs and nFETs, are a promising next-generation structure that achieves both area efficiency and high integration. Germanium (Ge) is a promising channel material with high carrier mobility, but challenges remain in terms of reliability and performance, such as increased interface trap density, high dislocation density in the epitaxial layer, and leakage current due to its narrow bandgap. This study proposes a vertically stacked CFET fabrication process using Ge nanosheets (NS) to overcome these challenges and reports on its operational demonstration.