[15a-S4_203-1~11] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[15a-S4_203-10] Study of Si interposer fabrication using minimal fab

〇Hiroyuki Tanaka¹, Hiroshi Tokunaga², Kayo Tanoue³, Shinji Iseki³, Shouichi Yasuda³, Yoshiyuki Nozawa⁴, Toshihiro Hayami⁴, Hiroshi Sugiyama⁵, Fumito Imura⁵, Miura Noriko¹, Shinichi Ikeda¹, Shiro Hara^1,5 (1.AIST, 2.MTC, 3.KB, 4.SPPT, 5.HS)

Keywords:

Interposer,Packaging,TSV

Advanced packaging technologies such as 3D stacking and chiplets have the potential to dramatically improve semiconductor performance through new technological innovations that incorporate front-end processes into chip integration techniques, previously a category of back-end processes. However, this process technology integration presents potential challenges due to the completely different substrate sizes and shapes involved, as well as the completely different systems involved in front-end and back-end processes. In the back-end process of minimal fabs, we are developing "FusionCore," which integrates multiple chips using front-end processes. This technology requires through-silicon via (TSV) etching on both sides of wafers when stacking multiple wafers. In some cases, a product called an interposer, or insertion substrate, is required to interconnect the electrodes between wafers fabricated with devices using TSV technology. Here, we report on our progress in prototyping a Si bridge process technology to connect stacked chips.