Session Details
[15a-S4_203-1~11]13.4 Si processing /Si based thin film / MEMS / Equipment technology
Sun. Mar 15, 2026 9:00 AM - 12:00 PM JST
Sun. Mar 15, 2026 12:00 AM - 3:00 AM UTC
Sun. Mar 15, 2026 12:00 AM - 3:00 AM UTC
S4_203 (South Bldg. 4)
[15a-S4_203-1]Development of Semiconductor Device Reconstruction Technology Using Minimal Fab
〇Ryuhei Sekifuji1, Hiroshige Kogayu1, Hiroshi Sugiyama1, Hiroyuki Tanaka2, Shuichi Noda2, Noriko Miura2, Shinichi Ikeda2, Hiroyuki Gomyo3, Ichiro Suzuki3, Shiro Hara1,2 (1.Hundred Semiconductors, 2.AIST, 3.Mach Corporation)
[15a-S4_203-2]Development of Multilayer Film Deposition Technology Using Minimal Fab
〇Ryuhei Sekifuji1, Hiroshige Kogayu1, Hiroyuki Tanaka2, Shuichi Noda2, Noriko Miura2, Shinichi Ikeda2, Hiroyuki Gomyo3, Ichiro Suzuki3, Shiro Hara1,2 (1.Hundred Semiconductors, 2.AIST, 3.Mach Corporation)
[15a-S4_203-3]SC1/SC2 chemical cleaning using wafer droplet cleaning technology
〇Kazumasa Nemoto1, Noriko Miura1, Shinichi Ikeda1, Shiro Hara1,2 (1.AIST, 2.Hundred)
[15a-S4_203-4]Application study of hydrogen-atmosphere surface-treatment using the Minimal laser heating tool to semiconductor CMOS devices(Ⅲ)
〇kazushige sato1,2, Takashi Chiba1,2, Masao Terada1,2, Kengo Hamada1,2, Yoshiaki Kanamori3, Noriko Miura4, Shinichi Ikeda4, Shiro Hara4 (1.MINIMAL, 2.SAKAGUCHI ELECTRIC HEATERS, 3.TOHOKU UNIV, 4.AIST)
[15a-S4_203-5]Formation of Ferroelectric HfNx Diodes Using Minimal Fab Reactive Sputtering Tool
〇Shuichi Noda1, Yuuki Yabuta2, Naoko Yamamoto2, Ryuichiro Kamei2, Noriko Miura1, Shinichi Ikeda1, Shun-ichiro Ohmi3, Shiro Hara1,4 (1.AIST, 2.Seinan-kogyo, 3.Science Tokyo, 4.Hundred)
[15a-S4_203-6]Development of 2-Layer Al Wiring and TiN gate for SOI-CMOS process in Minimal-Fab Process
〇Hiroshige Kogayu1, Ryuhei Sekifuji1, Hiroyuki Tanaka2, Noriko Miura2, Shiro Hara1,2 (1.Hundred, 2.AIST)
[15a-S4_203-7]Consideration of device design for manufacturing using Minimal Fab
〇Hiroyoshi Hongoh1, Noriko Miura1, Shinichi Ikeda1, Shiro Hara1,2 (1.AIST, 2.Hundred)
[15a-S4_203-8]Laser Microjet Cutting of 0.5-inch Wafers for Minimal Fab and ASIC Prototyping
〇Hirofumi Sumi1, Naonobu Shimamoto1, Yukinori Ochiai1, Shinji Tsuboi1, Tohru Mogami1, Yoshio Mita1, Hideharu Amano1, Atsutake Kosuge1, Makoto Ikeda1 (1.The University of Tokyo)
[15a-S4_203-9]Evaluation of wafer processing using Minimal Fab
〇Tatsuya Fujita1, Fumito Imura1, Kazushige Sato2, Shiro Hara1,3 (1.Inc.Hundred Semiconductors, 2.MINIMAL, 3.AIST)
[15a-S4_203-10]Study of Si interposer fabrication using minimal fab
〇Hiroyuki Tanaka1, Hiroshi Tokunaga2, Kayo Tanoue3, Shinji Iseki3, Shouichi Yasuda3, Yoshiyuki Nozawa4, Toshihiro Hayami4, Hiroshi Sugiyama5, Fumito Imura5, Miura Noriko1, Shinichi Ikeda1, Shiro Hara1,5 (1.AIST, 2.MTC, 3.KB, 4.SPPT, 5.HS)
[15a-S4_203-11]Impact of Minimal Water Plasma Ashing Process on Packaging Materials
〇Noriko Miura1, Erdenezaya Bat-Orgil2, Thiha Kyaw Swar2, Hnin Thazin Hlaing2, Hiroki Taniguchi2, Hiroshi Sugiyama3, Fumito Imura3, Takeshi Aizawa4, Mitsunori Nogawa4, Yasuhiro Onishi4, Tatsuo Ishijima2, Shinichi Ikeda1, Shiro Hara1,3 (1.AIST, 2.KANAZAWA Univ., 3.Hundred, 4.YONEKURA MFG. Co., LTD)
