Presentation Information

5:45 PM - 6:00 PM JST(8:45 AM - 9:00 AM UTC)

[15p-SL_101-15]Deposition Process Development of 40 nm Pt/(Al_0.9Sc_0.1)N/Pt Capacitor Stacks for Integration onto 300 mm Si Wafers

〇(D)Soshun Doko^1,2, Naoko Matsui¹, Toshikazu Irisawa¹, Koji Tsunekawa¹, Kazuki Okamoto², Hiroshi Funakubo² (1.Canon ANELVA, 2.Science Tokyo)

Keywords:

AlScN,logic-embedded memory,300 mm Si wafers

(Al,Sc)N films are being studied as promising materials for ferroelectric memory due to their large remanent polarization. To integrate ferroelectric materials in non-volatile memory devices, compatibility with 300 mm Si wafers widely used in advanced memory processes is essential. In this study, we evaluated Pt/(Al_0.9Sc_0.1)N/Pt capacitors with a total stack thickness of 40 nm deposited on 300 mm Si wafers.

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Presentation Information

[15p-SL_101-15]Deposition Process Development of 40 nm Pt/(Al0.9Sc0.1)N/Pt Capacitor Stacks for Integration onto 300 mm Si Wafers

Keywords:

[15p-SL_101-15]Deposition Process Development of 40 nm Pt/(Al_0.9Sc_0.1)N/Pt Capacitor Stacks for Integration onto 300 mm Si Wafers