[15p-W8E_101-1~13] 13.3 Insulator technology

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[15p-W8E_101-8] Improvement of TDDB in Sub-25 nm Gate-All-Around Vertical IGZO Transistor for 4F² DRAM

〇Akinori Kamiyama¹, Shoichi Kabuyanagi¹, Masaya Toda¹, Tomoharu Okada¹, Takamasa Hamai¹, Shosuke Fujii¹ (1.Kioxia Corporation)

Keywords:

semiconductor,DRAM,IGZO

Vertical channel transistors using IGZO channels have attracted attention for achieving high-density and low-power DRAM. However, the degradation factors of TDDB, especially related to new materials, processes, and vertical structures, are still not clarified. In this study, we revealed that the TDDB of scaled vertical channel transistor using IGZO channel can be degraded by a factor originating from the gate-all-around structure and factors related to the processes. Furthermore, we achieved a TDDB lifetime of over 10 years by suppressing the degradation factors related to the processes.