[16a-S2_203-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[16a-S2_203-7] Identification of Defective Location in TSV Structures for 3D Integrated Circuits Using the IR OBIRCH Method

〇(M1)Yujiro Takehara¹, Mizutani Naoki², Kouno Takurou³, Terasawa Yasuo³, Imura Fumito⁴, Akai Ichirou⁵, Aonishi Toru⁶, Hashishin Takeshi⁷ (1.GSST, Kumamoto Univ., 2.WDB Co., Ltd., 3.Nidek Co., Ltd., 4.Hundred Semiconductors Inc., 5.IINA, Kumamoto Univ., 6.GSFS, University of Tokyo., 7.FAST, Kumamoto Univ.)

Keywords:

through-silicon via (TSV),IR-OBIRCH Method,Minimal Fab

With the increasing demand for high-speed and large-capacity data transmission, improvement in the reliability of through-silicon vias (TSVs) has become increasingly important. In this study, the IR-OBIRCH method was applied to TSVs fabricated using a Minimal fab process, and electrical resistance changes induced by infrared laser irradiation were detected. Cross-sectional samples with and without scallops were prepared by varying the TSV formation conditions. As a result, clear differences in the IR-OBIRCH signal distribution depending on the sidewall morphology were observed, demonstrating that the locations of leakage current generation can be successfully identified.