Session Details
[16a-S2_203-1~9]13.5 Semiconductor devices/ Interconnect/ Integration technologies
Mon. Mar 16, 2026 9:00 AM - 11:45 AM JST
Mon. Mar 16, 2026 12:00 AM - 2:45 AM UTC
Mon. Mar 16, 2026 12:00 AM - 2:45 AM UTC
S2_203 (South Bldg. 2)
[16a-S2_203-1]The 17th Silicon Technology Division Paper Award / Young Researcher Award Ceremony
〇Osamu Nakatsuka1,2 (1.Chief Secretary of Silicon Technology Division, 2.Nagoya Univ.)
[16a-S2_203-2][The 17th Silicon Technology Division Paper Award Speech] Hole Mobility Enhancement in pMOSFETs Through High Ge Content, Asymmetric Strain and (110)-Oriented Channels
〇Chia-Tsong Chen1, Xueyang Han1, Kei Sumita1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Univ. of Tokyo)
[16a-S2_203-3][The 17th Silicon Technology Division Young Researcher Award] Intra-Grain Defect Formation via Discontinuous Solid-Phase Epitaxy
〇Manabu Tezura1, Takanori Asano1, Riichiro Takaishi1, Mitsuhiro Tomita1, Masumi Saitoh1, Hiroki Tanaka1 (1.Frontier Technology R&D Inst.)
[16a-S2_203-4][The 17th Silicon Technology Division Young Researcher Award] Temporary Direct Bonding by Low-Temperature Deposited SiO2 film
〇Koki Onishi1, Hayato Kitagawa1, Shunsuke Teranishi2, Akira Uedono3, Fumihiro Inoue1 (1.Yokohama National Univ., 2.DISCO corp., 3.Tsukuba Univ.)
[16a-S2_203-5]Analysis of the Correlation Between Dynamics and Edge-Void Formation in Wafer Bonding
〇Hyuga Ishii1, Ryota Ogata1, Taisuke Yamamoto1, Ryosuke Sato1, Hayato Kitagawa1, Fumihiro Inoue1 (1.Yokohama Nat Univ.)
[16a-S2_203-6]Process Optimization for High-Thermal Conductivity, Low-Temperature-Grown AlN for 3DIC/TSV by FM-CVD
〇(P)Yuhei Otaka1, Lu Yin-Chi1, Hatakeyama Daiki1, Jun Yamaguchi1, Tamaoki Naoki1, Noboru Sato1, Atsuhiro Tsukune1, Yukihiro Shimogaki1 (1.Univ. Tokyo)
[16a-S2_203-7]Identification of Defective Location in TSV Structures for 3D Integrated Circuits Using the IR OBIRCH Method
〇(M1)Yujiro Takehara1, Mizutani Naoki2, Kouno Takurou3, Terasawa Yasuo3, Imura Fumito4, Akai Ichirou5, Aonishi Toru6, Hashishin Takeshi7 (1.GSST, Kumamoto Univ., 2.WDB Co., Ltd., 3.Nidek Co., Ltd., 4.Hundred Semiconductors Inc., 5.IINA, Kumamoto Univ., 6.GSFS, University of Tokyo., 7.FAST, Kumamoto Univ.)
[16a-S2_203-8]Development of Planarized Resist Coating Technology for Deep Patterned Substrates
〇Haruki Kojima1, Hirotsugu Kawashima1, Sota Matsumoto1, Yusuke Okumura1, Akira Matsumura1, Koji Arita1 (1.KIOXIA Corporation)
[16a-S2_203-9]Suppression of Native Oxide in BaSi2 Solar Cells through HTL Engineering
〇Md Ariful Islam1, Yuka Fukaya1, Koki Hayashi1, Mizuki Hirai1, Yoichiro Koda2, Masami Mesuda2, Kaoru Toko1, Takashi Suemasu1 (1.Tsukuba Univ., 2.Tosoh Corp.)
