[16p-W8E_101-1~15] 13.7 Compound and power devices, process technology and characterization

4:15 PM - 4:30 PM JST(7:15 AM - 7:30 AM UTC)

[16p-W8E_101-9] Investigation of CO₂ Post-Oxidation Annealing Effects on the SiC–MOS Interface Using Mass-Production-Compatible Hot-Wall Oxidation Furnace

〇Mitsuru Sometani^1,2, Hirohisa Hirai¹, Naoki Kumagai¹, Hiroshi Yano³, Takanori Isobe³, Takuji Hosoi^2,4, Heiji Watanabe² (1.AIST, 2.UOsaka, 3.Univ. of Tsukuba, 4.NIMS)

Keywords:

SiC,CO2 POA,NBTI

In 4H-SiC MOS devices, gate-bias-induced threshold voltage (V_th) shift is an important issue, as it can lead to current imbalance, particularly during parallel operation. We have previously shown, using a laboratory-scale lamp furnace, that V_th shift can be reduced by applying an additional CO₂ post-oxidation anneal (POA) to SiC–MOS interfaces treated with conventional NO POA. In this study, we investigate the effect of CO₂ POA using a hot-wall oxidation furnace that is suitable for mass-production processes.