Presentation Information
[17a-S2_203-1]Development of shared processes for prototyping advanced FETs with the leading-edge-structures
〇Yoshihiro Hayashi1, Toshifumi Irisawa1, Wataru Mizubayashi1 (1.AIST)
Keywords:
a shared pilot line for elading-edge logic semicomductors,GAAFET,Selective epitaxial growth process of Si:P or SiGe:B
A gate-all-around (GAA) structure field-effective-transistor (FET) as of the cutting-edge logic semiconductors have been established for a shared pilot line that can be used by consortium member companies and others.
The essential processes include a silicon/silicon-germanium epitaxial film deposition process to form multi-stage silicon nanosheets, a selectively gas-chemical etching process for the silicon-germanium layer while leaving the silicon nanosheet layer, a selective epitaxial growth process of Si:P or SiGe:B in the GAAFET source/drain regions, and an atomic layer deposition (ALD) process to precisely adjust the thickness of the gate insulating film and work-function metal (WFM) film to control the transistor threshold voltage. These processes were newly developed in the AIST super clean room (SCR).
The essential processes include a silicon/silicon-germanium epitaxial film deposition process to form multi-stage silicon nanosheets, a selectively gas-chemical etching process for the silicon-germanium layer while leaving the silicon nanosheet layer, a selective epitaxial growth process of Si:P or SiGe:B in the GAAFET source/drain regions, and an atomic layer deposition (ALD) process to precisely adjust the thickness of the gate insulating film and work-function metal (WFM) film to control the transistor threshold voltage. These processes were newly developed in the AIST super clean room (SCR).