Session Details
[17a-S2_203-1~12]13.5 Semiconductor devices/ Interconnect/ Integration technologies
Tue. Mar 17, 2026 9:00 AM - 12:15 PM JST
Tue. Mar 17, 2026 12:00 AM - 3:15 AM UTC
Tue. Mar 17, 2026 12:00 AM - 3:15 AM UTC
S2_203 (South Bldg. 2)
[17a-S2_203-1]Development of shared processes for prototyping advanced FETs with the leading-edge-structures
〇Yoshihiro Hayashi1, Toshifumi Irisawa1, Wataru Mizubayashi1 (1.AIST)
[17a-S2_203-2]Gate Bias Dependence of Phonon-limited Electron Mobility in Si Nano-sheet MOSFET
〇Koichi Fukuda1, Junichi Hattori1, Yoshihiro Hayashi1 (1.AIST)
[17a-S2_203-3]Relationship between static characteristics and inner spacer length in Si nanosheet FETs
〇Junichi Hattori1, Koichi Fukuda1, Tsutomu Ikegami1, Atsushi Yagishita1, Yoshihiro Hayashi1 (1.AIST)
[17a-S2_203-4]3D In-line methodology in GAAFET fabrication process
〇Shin Kono1, Chia-Tsong Chen1, Kazuya Uejima1, Gansei Shichiri1, Atsushi Yagishita1, Toshifumi Irisawa1, Takashi Matsukawa1, Yoshihiro Hayashi1 (1.SFRC, AIST)
[17a-S2_203-5]Simultaneous formation of dummy gates for GAAFET using Self-Aligned Double Patterning (SADP) and wide lithography patterning
〇Hiroki Tonegawa1, Tetsuya Ueda1, Motoharu Shichiri1, Hironori Yamamoto1, Yoshihiro hayashi1 (1.AIST SFRC)
[17a-S2_203-6]23nm-wide Gate Patterning by Electron Beam Lithography using a Tone Reversal Process (EB-R) Highly Compatible to Self-Aligned Double Patterning (SADP) Process
〇SUNGWON YOUN1, Tetsuya Ueda1, Motoharu Shichiri1, Junichi Furukawa1, Kazuyuki Matsumaro1, Iijima Syuuichi1, Noguchi Yoshiji1, Sugiyama A1, Hayashi Yoshihiro1 (1.AIST)
[17a-S2_203-7]Evaluation of dual damascene patterning by nanoimprint lithography
〇Ryosuke Hamamoto1, Kenta Suzuki1, Tetsuya Ueda1, Yoshihiro Hayashi1, Wataru Mizubayashi1, Atsushi Kusaka2, Masaki Ishida2, Kidai Sogo2, Tomomi Funayoshi2, Masayuki Kagawa2, Makoto Ogusu2, Noriyasu Hasegawa2, Kiyohito Yamamoto2 (1.AIST SFRC, 2.Canon)
[17a-S2_203-8]Reduction of leakage current of HfO2 gate stacks by low thermal budget FLA
〇Hayato Watanabe1, Katsuhiro Mitsuda1, Yuito Maki1, Yukinori Morita2, Hiroyuki Ota2, Yoshihiro Hayashi2, Shinichi Kato1, Takumi Mikawa1 (1.SCREEN Semiconductor Solutions, 2.SFRC AIST)
[17a-S2_203-9]Evaluation of growth rate of SiP for source/drain formation in NMOS-GAAFET
〇Naoto Kumagai1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1.AIST)
[17a-S2_203-10]Process development for fabricating Si nanosheet GAAFET on 300 mm wafers: Selective epitaxial growth and channel release
〇CHIATSONG CHEN1, Toshihiro Narushima1, Shin Kono1, Kazuya Uejima1, Atsushi Yagishita1, Naoto Kumagai1, Takahiro Goya1, Ryutaro Nishino1, Kenzou Manabe1, Yoko Tanaka1, Masanaga Fukasawa1, Yuuki Ishida1, Yukinori Morita1, Hiroyuki Ota1, Toshifumi Irisawa1, Wataru Mizubayashi1, Takashi Matsukawa1, Yoshihiro Hayashi1 (1.AIST)
[17a-S2_203-11]Investigation of Selective Source/Drain epitaxial growth for CMOS-GAAFET Integration
〇Yoko Tanaka1, Hiroki Tonegawa1, Ryutaro Nishino1, Kazuya Uejima1, Naoto Kumagai1, Tetsuya Ueda1, Chia-Tsong Chen1, Toshifumi Irisawa1, Atsushi Yagishita1, Yoshihiro Hayashi1 (1.AIST SFRC)
[17a-S2_203-12]Analysis of Parasitic Series Resistance Effect in Gate-All-Around FETs by a Modified Alpha-Power Law Model
〇Kazuya Uejima1, Atsushi Yagishita1, Naoto Kumagai1, Chia-Tsong Chen1, Masanaga Fukasawa1, Shutaro Asanuma1, Toshihiro Kamei1, Yuuki Ishida1, Naoya Okada1, Kenzo Manabe1, Yuji Kasashima1, Yukinori Morita1, Toshifumi Irisawa1, Wataru Mizubayashi1, Hiroyuki Ota1, Fuminori Ito1, Takashi Matsukawa1, Yoshihiro Hayashi1 (1.SFRC, AIST)