[17a-S2_203-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)

[17a-S2_203-12] Analysis of Parasitic Series Resistance Effect in Gate-All-Around FETs by a Modified Alpha-Power Law Model

〇Kazuya Uejima¹, Atsushi Yagishita¹, Naoto Kumagai¹, Chia-Tsong Chen¹, Masanaga Fukasawa¹, Shutaro Asanuma¹, Toshihiro Kamei¹, Yuuki Ishida¹, Naoya Okada¹, Kenzo Manabe¹, Yuji Kasashima¹, Yukinori Morita¹, Toshifumi Irisawa¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Fuminori Ito¹, Takashi Matsukawa¹, Yoshihiro Hayashi¹ (1.SFRC, AIST)

Keywords:

Gate-all-around (GAA) FET,Parasitic series resistance,Alpha-power law model

A new methodology to analysis parasitic series resistance (R_pr) for gate-all-around FET (GAAFET) is proposed. The α power law model based on the drain current is modified to an implicit function, considering the loss of gate voltage by I_dsR_pr drop. A modified α power model enables a simple R_pr extraction strategy from experimental I_ds–V_gs characteristic of GAAFETs obtained in both linear and saturation regions. Our methodology is useful to analyze the critical resistance parameter for highly scaled three-dimensional devices.