[17a-S2_203-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[17a-S2_203-3] Relationship between static characteristics and inner spacer length in Si nanosheet FETs

〇Junichi Hattori¹, Koichi Fukuda¹, Tsutomu Ikegami¹, Atsushi Yagishita¹, Yoshihiro Hayashi¹ (1.AIST)

Keywords:

nanosheet,device simulation,TCAD