[17a-S2_203-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[17a-S2_203-7] Evaluation of dual damascene patterning by nanoimprint lithography

〇Ryosuke Hamamoto¹, Kenta Suzuki¹, Tetsuya Ueda¹, Yoshihiro Hayashi¹, Wataru Mizubayashi¹, Atsushi Kusaka², Masaki Ishida², Kidai Sogo², Tomomi Funayoshi², Masayuki Kagawa², Makoto Ogusu², Noriyasu Hasegawa², Kiyohito Yamamoto² (1.AIST SFRC, 2.Canon)

Keywords:

NIL,semiconductor

We are investigating the feasibility of applying nanoimprint lithography (NIL) to pattern formation in the dual-damascene (DD) interconnect process. Interconnect and via resist patterns formed simultaneously by NIL were successfully transferred to the underlying layer through etching, followed by copper filling. The transferred patterns exhibited good fidelity, and no voids were observed in the copper fill. These results demonstrate the potential of NIL as a promising candidate technology for enabling a DD interconnect process. In this presentation, we will describe the evaluation methodology, present the current progress, and discuss the remaining challenges.