[17a-S2_203-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[17a-S2_203-9] Evaluation of growth rate of SiP for source/drain formation in NMOS-GAAFET

〇Naoto Kumagai¹, Toshifumi Irisawa¹, Yoshihiro Hayashi¹ (1.AIST)

Keywords:

NMOS-GAAFET,SiP