[17a-S4_203-1~11] 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[17a-S4_203-10] Simulation and Modelling of Single Event Upset in CFET SRAM

〇(BC)Vanness Filbert Cierra¹, Yoshinari Kamakura¹ (1.Osaka Inst. Tech.)

Keywords:

device simulation,soft error,CFET

Soft errors caused by the incidence of radiation on the transistor is recognized as one of the serious problems related to the reliability of integrated circuits. CFET, which is considered a promising technology for next-generation semiconductors, is expected to increase the possibility of radiation passing through multiple transistors at the same time in the future. In this study, we used TCAD and SPICE simulations to analyze the occurence of Single Event Upset (SEU) in CFET SRAM and investigate the physical mechanism behind it. Furthermore, a model for predicting the occurrence of errors was also examined.