[18a-S2_203-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[18a-S2_203-7] A Study on Probabilistic Non-volatile Memory Cells Utilizing Intrinsic Noise in Nanowires

〇(B)Kenshin Takamura¹, Kota Ando², Katsuhiro Tomioka², Tetsuya Asai² (1.School of Engineering, Hokkaido Univ., 2.Faculty of Information Science and Technology, Hokkaido Univ.)

Keywords:

stochastic memory,ReRAM,nanowires

To achieve low-power edge AI through stochastic computing (SC), we propose a stochastic memory cell using random telegraph noise (RTN) of nanowires (NWs) and resistive random-access memory (ReRAM). The RTN is converted into multi-level noise with an offset adjusted by the ReRAM, and stochastic logic 0/1 outputs are obtained by comparison using a CMOS latch. SPICE analysis confirms that the probability of logic 1 output is controllable by varying the ReRAM resistance.