[3D01-07] Electrode Surface Science

11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[3D06] Operando detection of trapped holes at the interface of molecular layer EDL-FET by EC-ATR-UV and its relation with bias stress of the device

Tatsuya Ogawa¹, Daiki Yoshino¹, Ichiro Tanabe², Pushi Wang³, Jun Takeya³, *Ken-ichi Fukui¹ (1. The University of Osaka (Japan), 2. Rikkyo University (Japan), 3. The University of Tokyo (Japan))

Electric double layer organic field-effect transistors (EDL-OFETs) using ionic liquid (IL) as a gate insulator are advantageous because of their significantly low operation gate voltage. High electric field of EDL enables facile hole carrier accumulation and transport of the carrier at the IL/organic semiconductor interface, but may also cause the carrier hole trap, which we previously proposed as a major origin of the bias stress (shift of the operation gate voltage) of the FET device. To identify the hole carrier, interface sensitive operando technique of attenuated total reflection (ATR) in UV region under electrochemical control (EC-ATR-UV) was successfully adapted for two molecular layers of C9-DFBDT-NW film fabricated on the ATR prism. By repeating the on-off cycles of the FET for a few hundred times or keeping the ‘on’ state gate voltage for 1-30 min, ‘trapped holes’ were successfully detected at ‘off’ state gate voltage by EC-ATR-FUV. The amount of trapped holes gradually decreased in the time scale of several hundred seconds. A model for the shift of the operation voltage and the roll of the trapped hole will be discussed.

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