2024 International Conference on Solid State Devices and Materials
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Session Details

Short Courses

[SC2]Sustainable CMOS Scaling towards 0.5nm Node Era

Sun. Sep 1, 2024 10:25 AM - 4:00 PM JST
Sun. Sep 1, 2024 1:25 AM - 7:00 AM UTC
Room B & C (408 & 409)(4th Floor)
Organizer: Meishoku Masahara (AIST)
Chair: Wataru Mizubayashi (AIST)
10:25 AM - 10:30 AM JST(1:25 AM - 1:30 AM UTC)

[SC2-OP]Opening Remarks

10:30 AM - 11:15 AM JST(1:30 AM - 2:15 AM UTC)

[SC2-01]Advanced Compute Scaling with Nanosheet-based Devices and Increased Interdisciplinary Synergies

〇Anabela Veloso1 (1. imec)
11:15 AM - 12:00 PM JST(2:15 AM - 3:00 AM UTC)

[SC2-02]2D layered semiconductor FETs : Challenge & Perspective

〇Kosuke Nagashio1 (1. The Univ. of Tokyo)
12:00 PM - 12:45 PM JST(3:00 AM - 3:45 AM UTC)

Lunch Break

12:45 PM - 1:30 PM JST(3:45 AM - 4:30 AM UTC)

[SC2-03]How could the "Open Source Silicon" movement drive Device and Materials development?

〇Junichi Okamura1 (1. AIST Solutions Co., Ltd.)
1:30 PM - 2:15 PM JST(4:30 AM - 5:15 AM UTC)

[SC2-04]Silicon-based Integrated Photonics

〇Tsuyoshi Horikawa1 (1. Tokyo Tech)
2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

Break

2:30 PM - 3:15 PM JST(5:30 AM - 6:15 AM UTC)

[SC2-05]Metrology challenges for future CMOS scaling

〇Makoto Suzuki1 (1. Hitachi High-Tech Corp.)
3:15 PM - 4:00 PM JST(6:15 AM - 7:00 AM UTC)

[SC2-06]Cryogenic CMOS Device Technology for Quantum Computing Application

〇Hiroshi Oka1 (1. AIST)
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