Session Details
[F-4]AI Computing Circuits
Wed. Sep 17, 2025 10:45 AM - 12:00 PM JST
Wed. Sep 17, 2025 1:45 AM - 3:00 AM UTC
Wed. Sep 17, 2025 1:45 AM - 3:00 AM UTC
Room F (312, 3rd Floor)
Session Chair: Nobuhiko Nakano (Keio Univ.), Yitao Ma (Zhejiang Univ.)
[F-4-01]Crystal Indium Oxide Memory Macro for Analog in-Memory Computing System on Chip, Achieving 13.4-μW Power and 417.8-TOPS/W Efficiency
〇Kiyotaka Kimura1, Yusuke Komura1, Kazuma Furutani1, Kazuki Tsuda1, Yoshinori Ando1, Motomu Kurata1, Tsutomu Murakawa1, Takanori Matsuzaki1, Tatsuya Onuki1, Yuto Yakubo1, Shunpei Yamazaki1 (1. Semiconductor Energy Laboratory Co., Ltd. (Japan))
[F-4-02]Hybrid-Domain SRAM Computation-in-Memory Architecture for Mixed-Precision FP/INT Operations
〇Ruhui Liu1, Yufan Zhang1, Naoko Misawa1, Chihiro Matsui1, Ken Takeuchi1,2 (1. Dept. of Electrical Eng. and Info. Systems, The Univ. of Tokyo (Japan), 2. Systems Design Lab., Grad. School of Eng., The Univ. of Tokyo (Japan))
[F-4-03]Truncated Carry Approximate Adder and Explicit Bit Pruning for SRAM-based Digital Computation-in-Memory
〇Daqi LIN1, Tao Wang1, Ruhui Liu1, Naoko Misawa1, Chihiro Matsui1, Ken Takeuchi2 (1. Dept. of Electrical Eng. and Info. Systems, The Univ. of Tokyo (Japan), 2. Systems Design Lab., Grad. School of Eng., The Univ. of Tokyo (Japan))
[F-4-04]High-Efficient Automatic White Balance Circuit Engine using Ultra-lightweight Half-SqueezeNet-DSC Architecture with Self-Attention Mechanism
〇Hanfeng Wang1, Zhaolong He2, Yue Cheng1, Hongbo Zhu4, Dawei Gao1, Wenzhang Fang1,3, Yitao Ma1,3 (1. Zhejiang University (China), 2. University of Science and Technology of China (China), 3. ZJU-Hangzhou Global Scientific and Technological Innovation Center (China), 4. Hangzhou Miaoxinqiu Technology, Ltd (China))