2025 International Conference on Solid State Devices and Materials
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Session Details

Short Courses

[SC1]Symphony of Circuits and Devices for the AI Era

Mon. Sep 15, 2025 12:55 PM - 4:45 PM JST
Mon. Sep 15, 2025 3:55 AM - 7:45 AM UTC
314 & 313, 3rd Floor
Organizers: Hiromi Yuasa (Kyushu Univ.), Kosuke Miyaji (Shinshu Univ.), Takeaki Yajima (Kyushu Univ.)
12:55 PM - 1:00 PM JST(3:55 AM - 4:00 AM UTC)

[SC1-OP]Opening Remarks

1:00 PM - 1:35 PM JST(4:00 AM - 4:35 AM UTC)

[SC1-01]STT/SOT-MRAM and Low Power AI Processor/Computing as Its Application

〇Tetsuo Endoh1 (1. Tohoku Univ.)
1:35 PM - 2:10 PM JST(4:35 AM - 5:10 AM UTC)

[SC1-02]Memory-Centric Computing Circuits for AI Applications

〇Ken Takeuchi1 (1. The Univ. of Tokyo)
2:10 PM - 2:45 PM JST(5:10 AM - 5:45 AM UTC)

[SC1-03]Si programmable photonic integrated circuits for photonic AI processors

〇Mitsuru Takenaka1 (1. The Univ. of Tokyo)
2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)

Break

3:00 PM - 3:35 PM JST(6:00 AM - 6:35 AM UTC)

[SC1-04]Energy-Efficient AI Accelerators with Hardware-Friendly Models for Inference Era

〇Hiroshi Fuketa1 (1. AIST)
3:35 PM - 4:10 PM JST(6:35 AM - 7:10 AM UTC)

[SC1-05]TBD

〇Jun Deguchi1 (1. KIOXIA)
4:10 PM - 4:45 PM JST(7:10 AM - 7:45 AM UTC)

[SC1-06]Stochastic in-memory AI computing circuits

〇Tetsuya Asai1 (1. Hokkaido Univ.)
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