[A-1] DTCO

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[A-1-03] Enhancing SRAM Design with A Novel Staggered-Gate CFET: A Path to Area Reduction and Performance Optimization

〇Xin Wang^1,2, Longyu Sun^1,2, Haoyan Liu^1,2, Yongliang Li^1,2 (1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Inst. of Microelectronics of the Chinese Academy of Sciences (China), 2. School of Integrated Circuits, Univ. of Chinese Academy of Sciences (China))