[A-1] DTCO | 2026 International Conference on Solid State Devices and Materials

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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-1]DTCO

Tue. Sep 15, 2026 1:15 PM - 3:00 PM JST
Tue. Sep 15, 2026 4:15 AM - 6:00 AM UTC

Room A(Convention Hall 1, 2rd Floor)

Session Chair:Kuniyuki Kakushima(Institute of Science Tokyo), Genji Nakamura(Tokyo Electron Ltd.)

1:15 PM - 1:45 PM JST(4:15 AM - 4:45 AM UTC)

[A-1-01 (Invited)]Holistic System and Technology Co-Optimization for High-Performance Edge AI Computing Platforms

〇Youseok Suh¹, Jie Deng¹, Jun Yuan¹, Frank Yang¹, Jihong Choi¹, Milind Shah¹, Pranjal Srivastava¹, Giri Nallapati¹, PR. Chidi Chidambaram¹ (1. Qualcomm (USA))

1:45 PM - 2:00 PM JST(4:45 AM - 5:00 AM UTC)

[A-1-02]DTCO Investigation of Self-Aligned Backside-Contact Monolithic CFET with BM0-signal and M0-power Routing at Standard-Cell-Library Level

〇Yuxuan Wang¹, Yaoping Xiao¹, Jinhyun Chun¹, Masaharu Kobayashi¹ (1. The University of Tokyo (Japan))

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[A-1-03]Enhancing SRAM Design with A Novel Staggered-Gate CFET: A Path to Area Reduction and Performance Optimization

〇Xin Wang^1,2, Longyu Sun^1,2, Haoyan Liu^1,2, Yongliang Li^1,2 (1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Inst. of Microelectronics of the Chinese Academy of Sciences (China), 2. School of Integrated Circuits, Univ. of Chinese Academy of Sciences (China))

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[A-1-04]Self-Heating Characterization and Thermal Network Modeling of Sequential CFET with Backside Power Delivery Network

〇Taoyu Zhou¹, Naiqi Liu¹, Yandong He¹, Gang Du^1,2 (1. Peking Univ. (China), 2. Beijing Innovation Center of Integrated Circuits Lab. (China))

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[A-1-05]A DTCO Examination and Optimization on PowerVia Technology on GAA

〇Chuangxin Zhou¹, Feiyu Teng¹, Xiangyu Yan¹, Rui Guo¹, Ziqiao Xu¹, Runsheng Wang¹, Ming Li¹, Heng Wu¹ (1. Peking University (China))

2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)

[A-1-06]Geometry-Dependent Thermal Network Model for Flip-FET

〇Naiqi Liu¹, Taoyu Zhou¹, Yandong He¹, Gang Du¹ (1. School of Integrated Circuits, Peking Univ. (China))

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