[A-2] Gate stack engineering 1

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[A-2-03] Impact of Ultrathin Oxygen-Passivated Interfacial Layer on Electron Mobility of MOSFETs in Scaled CET Regime

〇Yukinori Morita^1,6, Takamasa Kawanago^1,6, Takefumi Kamioka^1,2,6, Yuichiro Mitani^2,6, Toshihide Nabatame^3,6, Takashi Onaya^3,6, Naoki Fukata^3,6, Wipakorn Jevasuwan^3,6, Kazuhito Tukagoshi^3,6, Takuya Hoshii^4,6, Kasidit Toprasertpong^5,6, Atsushi Tamura^5,6, Koji Kita^5,6, Naoya Okada^1,6, Kenzo Manabe^1,6, Wataru Mizubayashi^1,6, Hiroyuki Ota^1,6, Takashi Matsukawa^1,6, Shinji Migita^1,6 (1. AIST (Japan), 2. Tokyo City Univ. (Japan), 3. NIMS (Japan), 4. Sci. Tokyo (Japan), 5. The Univ. Tokyo (Japan), 6. LSTC (Japan))