[A-2] Gate stack engineering 1 | 2026 International Conference on Solid State Devices and Materials

Advanced Search

Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-2]Gate stack engineering 1

Tue. Sep 15, 2026 3:30 PM - 5:00 PM JST
Tue. Sep 15, 2026 6:30 AM - 8:00 AM UTC

Room A(Convention Hall 1, 2rd Floor)

Session Chair:Genji Nakamura(Tokyo Electron Ltd.), Woo Young Choi(Seoul National Univ.)

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

[A-2-01]Effect of Annealing Temperature on Ultra-thin EOT of HfZrON Gate Dielectrics with Nitrogen Plasma Treatment

〇Zhaohao Zhang^1,2, Kun Zhong^1,2, Junfeng Li^1,2, Huaxiang Yin^1,2 (1. Institute of Microelectronics of the Chinese Academy of Sciences (China), 2. University of Chinese Academy of Sciences (China))

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)

[A-2-02]Decoupling of Time to Breakdown and Charge to Breakdown via Area Scaling in HfO₂ Gate Stacks with TiAlC and Bottom TiN Insertion

〇Hiroyuki Ota¹, Yukinori Morita¹, Kenzo Manabe¹, Misako Morota¹, Naoya Okada¹, Kazuya Uejima¹, Shinji Migita¹, Yoshihiro Hayashi¹ (1. AIST (Japan))

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[A-2-03]Impact of Ultrathin Oxygen-Passivated Interfacial Layer on Electron Mobility of MOSFETs in Scaled CET Regime

〇Yukinori Morita^1,6, Takamasa Kawanago^1,6, Takefumi Kamioka^1,2,6, Yuichiro Mitani^2,6, Toshihide Nabatame^3,6, Takashi Onaya^3,6, Naoki Fukata^3,6, Wipakorn Jevasuwan^3,6, Kazuhito Tukagoshi^3,6, Takuya Hoshii^4,6, Kasidit Toprasertpong^5,6, Atsushi Tamura^5,6, Koji Kita^5,6, Naoya Okada^1,6, Kenzo Manabe^1,6, Wataru Mizubayashi^1,6, Hiroyuki Ota^1,6, Takashi Matsukawa^1,6, Shinji Migita^1,6 (1. AIST (Japan), 2. Tokyo City Univ. (Japan), 3. NIMS (Japan), 4. Sci. Tokyo (Japan), 5. The Univ. Tokyo (Japan), 6. LSTC (Japan))

4:15 PM - 4:30 PM JST(7:15 AM - 7:30 AM UTC)

[A-2-04]Leakage current and EOT reduction of HfSiOx Gate Dielectric via Controlled Nitridation Using Millisecond Flash Lamp Annealing

〇Yuito Maki¹, Hayato Watanabe¹, Hideaki Tanimura¹, Katsuhiro Mitsuda¹, Shinichi Kato¹, Takumi Mikawa¹, Yasuo Nara² (1. SCREEN Semiconductor Solutions Co., Ltd. (Japan), 2. Tokyo City University (Japan))

4:30 PM - 4:45 PM JST(7:30 AM - 7:45 AM UTC)

[A-2-05]TiN Thickness Scaling as a Lever for Interlayer Scavenging: Gate Stack Performance and Reliability Perspectives

〇Elhadji Alhousseyni Diallo¹, Tadeu Mota Frutuoso¹, William Vandendaele¹, Rèmy Gassilloud¹, Elise Arnoux¹, Laurent Brevard¹, Claire Fenouillet-Beranger¹, Marie-claire Cyrille¹, Xavier Garros (1. Univ. Grenoble Alpes, CEA-Leti (France))

4:45 PM - 5:00 PM JST(7:45 AM - 8:00 AM UTC)

[A-2-06]Mitigating BTI Degradation in HKMG Transistors via Oxygen Reservoir Layer Engineering

〇Kyungwook Park^1,2, Changhwan Choi¹, Sangkuk Han¹, Wonjae Choi¹, Haesoo Jang¹, Jaewon Chung¹, Sangmyun Lim¹, Sangwoo Jung¹, Soyoung Park¹ (1. Hanyang Univ. (Korea), 2. Samsung Electronics Corp., Ltd. (Korea))

Back to Category List