[A-3] Gate stack engineering 2

9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[A-3-04] Dipole-Middle Scheme Enabled V_FB Tuning with Reduced Thermal Budget in La₂O₃/HfO₂ Gate Stack

〇Xingrong Xiao^1,2, Haoyan Liu¹, Yongliang Li¹ (1. State Key Laboratory of Fabrication Technologies for Integrated Circuits, Inst. of Microelectronics of the Chinese Academy of Sciences (China), 2. School of Advanced Interdisciplinary Sciences, Univ. of Chinese Academy of Sciences (China))