[A-5] GAA FET

8:45 AM - 9:00 AM JST(11:45 PM - 12:00 AM UTC)

[A-5-02] Process Optimization of GAAFET CMOS for Leakage Current Reduction

〇Kazuya Uejima¹, Atsushi Yagishita¹, Naoto Kumagai¹, Chia-Tsong Chen¹, Masanaga Fukasawa¹, Shutaro Asanuma¹, Toshihiro Kamei¹, Yuuki Ishida¹, Naoya Okada¹, Kenzo Manabe¹, Yuji Kasashima¹, Hiroki Tonegawa¹, Shin Kono¹, Tetsuya Ueda¹, Motoharu Shichiri¹, Ryutaro Nishino¹, Yoko Tanaka¹, Takahiro Goya¹, Jun'ichi Hattori¹, Yukinori Morita¹, Toshifumi Irisawa¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Fuminori Ito¹, Takashi Matsukawa¹, Yoshihiro Hayashi¹ (1. National Inst. of AIST (Japan))