2026 International Conference on Solid State Devices and Materials
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Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-5]GAA FET

Thu. Sep 17, 2026 8:30 AM - 9:45 AM JST
Thu. Sep 17, 2026 11:30 PM - 12:45 AM UTC
Room A(Convention Hall 1, 2rd Floor)
Session Chair:Francois Andrieu(CEA-Leti), Heng Wu(Peking Univ.)
8:30 AM - 8:45 AM JST(11:30 PM - 11:45 PM UTC)

[A-5-01]Standard Cell Performance Improvement with Ultra Low Temperature (<350°C) SiGe:B GAA Si Nanosheet P-FET

〇Arka Dutta1, Ritam Sarkar1, Pierre Eyben1, Daniel Casey2, Hiroaki Arimura1, Thomas Chiarella1, Anabela Veloso1, Andrea Pondini1,3, Alexander Makarov1, Lynn Verschueren1, Hans Mertens1, Clement Porret1, Thomas Dursap1, Jishnu Ganguly1, Conor Cullen2, Rami Khazaka2, Min Soo Kim1, Lucas Petersen Barbosa Lima1, Jerome Mitard1, Serge Biesemans1, Naoto Horiguchi1 (1. imec (Belgium), 2. ASM (Belgium), 3. KU Leuven (Belgium))
8:45 AM - 9:00 AM JST(11:45 PM - 12:00 AM UTC)

[A-5-02]Process Optimization of GAAFET CMOS for Leakage Current Reduction

〇Kazuya Uejima1, Atsushi Yagishita1, Naoto Kumagai1, Chia-Tsong Chen1, Masanaga Fukasawa1, Shutaro Asanuma1, Toshihiro Kamei1, Yuuki Ishida1, Naoya Okada1, Kenzo Manabe1, Yuji Kasashima1, Hiroki Tonegawa1, Shin Kono1, Tetsuya Ueda1, Motoharu Shichiri1, Ryutaro Nishino1, Yoko Tanaka1, Takahiro Goya1, Jun'ichi Hattori1, Yukinori Morita1, Toshifumi Irisawa1, Wataru Mizubayashi1, Hiroyuki Ota1, Fuminori Ito1, Takashi Matsukawa1, Yoshihiro Hayashi1 (1. National Inst. of AIST (Japan))
9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)

[A-5-03]Insights into Ultra-Scaled Nanosheet FETs for the Angstrom Era

〇Anabela Veloso1, Ruben Asanovski1, Jeroen E. Scheerder1, Daniel Casey2, Conor Cullen2, Clement Porret1, Thomas Dursap1, Geert Eneman1, Felix Seidel1, Claudia Fleischmann1, Paola Favia1, Ritam Sarkar1, Arka Dutta1, Xiuju Zhou1, Anne Vandooren1, Roger Loo1, Rami Khazaka2, Naoto Horiguchi1 (1. imec (Belgium), 2. ASM (Belgium))
9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[A-5-04]A Novel Trench-Free SiGe Channel GAA Nanosheet Transistor with Reduced Gate Capacitance and Improved Circuit Performance

〇Fei Zhao1, Haoyan Liu1, Xiaofeng Jia1, Yan Li2, Yongliang Li1 (1. Inst. of Microelectronics, Chinese Academy of Science (China), 2. Beijing Information Science and Technology University (China))
9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[A-5-05]Sub-Nanometer Tomographic Imaging of Resistance, Carrier Distribution and Effective Gate Length in 45 nm Gate Pitch Nanosheet-FETs

〇Andrea Pondini1,2, Pierre Eyben2, Lennaert Wouters2, Hiroaki Arimura2, Thomas Chiarella2, Hans Mertens2, Arka Dutta2, Albert Minj2, Clement Porret2, Erik Rosseel2, Philippe Matagne2, Thomas Hantschel2, Naoto Horiguchi2, Jérôme Mitard2, Anne Verhulst1,2 (1. KU Leuven (Belgium), 2. imec (Belgium))
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