[A-6] Advanced CMOS process

11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[A-6-03] Optimization of vertically stacked n-NSFET combining experimental access re-sistance extraction and TCAD analysis.

〇Pierre Eyben EYBEN¹, An De Keersgieter¹, Maryam Hosseini¹, Andrea Pondini^1,2, Arka Dutta¹, Hiroaki Arimura¹, Thomas Chiarella¹, Elena Capogreco¹, Philippe Matagne¹, Jérôme Mitard¹, Naoto Horiguchi¹ (1. IMEC (Belgium), 2. KU Leuven (Belgium))