[B-3] DRAM 1

9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[B-3-05 (Late News)] Optimizing Bits/Cell of Weight and Input for MAC Operation with 2T0C DRAM

〇Aman Chandrakar¹, Rohit Kumar Nirala¹, Manish Gupta², Abhinav Kranti¹ (1. Indian Inst. of Tech. Indore (India), 2. BITS Pilani K K Birla Goa Campus (India))