[B-7] Flash Memory and Emerging Memory Devices

12:45 PM - 1:00 PM JST(3:45 AM - 4:00 AM UTC)

[B-7-01] Asymmetric Dual-Gate Biasing for Optimal Balancing of Read Speed and Program Efficiency in NAND Flash Memory

〇Kwanyong Kim^1,2,3, Devin Verreck^1,2, Kruti Trivedi¹, Laurent Breuil¹, Tathagata Paul², Christophe Lorant¹, Geert Van den bosch¹, Jo De Boeck^1,2, Maarten Rosmeulen^1,2 (1. IMEC (Belgium), 2. KU(Katholieke Univ.) Leuven (Belgium), 3. Samsung Electronics (Korea))